Over the recent years, a copper wiring has been adopted as a wiring material for Complementary Metal Oxide Semiconductor (CMOS) Large Scale Integration (LSI) in terms of reducing wiring resistance and enhancing durability against electromigration (EM) and stress migration (SM).
Copper (Cu) is, unlike aluminum (Al) which has hitherto been used, difficult of working the wiring by dry etching. Then, formation of the copper wiring generally involves adopting a damascene method of forming a trench serving as the wiring and a via serving as a contact in an insulating film and forming the wiring by embedding the copper therein, and a dual damascene method of forming the trench serving as the wiring and the via, and integrally forming the wiring and a plug by embedding the copper therein. An copper electroplating method is generally adopted in terms of productivity and costs on the occasion of growing the copper wiring layer.
The electroplated copper film (Cu electroplating deposition layer) based on the damascene method is mixed with impurities such as oxygen (O), carbon (C), sulfur (S), chlorine (CI) and nitrogen (N), and it is known that impurities in the wiring affect the durability against the EM, the SIV, etc (refer to, e.g., Non-Patent documents 1 and 2).
In a copper wiring forming process based on a general Cu/Ta(N) wiring structure, the EM and the SIV are in a tradeoff-relationship. Namely, if the wiring has a narrow width, a problem is the durability against the EM but is solved by decreasing concentration of impurities. While on the other hand, if the wiring has the wide width, the problem is the durability against the SIV but is solved by increasing the concentration of impurities.
Accordingly, concentration of impurities is desired to be adjusted corresponding to the wiring width on the occasion of forming the copper wiring. Note that impurities in the copper plated film is thermally diffused by an annealing step after plating, and it is therefore preferable to make an adjustment of concentration of impurities, which includes this diffusion behavior.
Note that Patent document 1 discloses a technology for solving a decline of the EM durability due to a decrease in concentration of impurities that occurs when forming the copper wiring layer in a way that applies low power to the wafer at a first power level for a first time period; and positively pulsing a second power to the wafer during a second time period following the first time period, the second power having on time periods and off time periods, and solving occurrence of a void between the copper wiring layer and a seed layer, which is caused when forming the copper wiring layer by applying the low power. Namely, the technology discussed in Patent document 1 improves electric characteristics of the copper wiring layer by gaining a balance between the decrease quantity of concentration of impurities and the occurrence quantity of the void.
Further, Patent document 2 discloses a scheme of adjusting concentration of impurities of the plated copper by changing a magnitude of the electric current during the electroplating.    [Non-Patent document 1] Influence of Copper Purity on Microstructure and Electromigration. B. Alers, et al. (IEEE 2004)    [Non-Patent document 2] Design of ECP Additive for 65 nm-node Technology Cu BEOL Reliability, H. Shih, et al., (ITC 2005)    [Patent document 1] Japanese Patent Laid-Open Publication No. 2000-353675    [Patent document 2] Japanese Patent Laid-Open Publication No. 2006-32545